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16 Mbit LPC Serial Flash
A Microchip Technology Company
SST49LF016C
Data Sheet
AAI Data Load Protocol
Table 19: AAI Programming Cycle (initiated with WP#/AAI at V H ONLY)
Clock
Cycle
Field Name Field Contents LAD[3:0]
Comments
1
START
1110
IN
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized. The START field contents
indicate a Firmware Memory Write cycle. (1110b)
2
IDSEL
0000b to 1111b IN
ID works identically to Firmware Memory cycle.
This field indicates which SST49LF016C device
should respond. If the IDSEL (ID select) field matches
the value of ID[3:0], then that particular device will
respond to the whole bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
Only bits [20:7] of the total address [27:0] are used for
AAI mode. The rest are “don’t care”.
10
11-266
MSIZE
DATA
KKKK
ZZZZ
IN
IN
MSIZE field is don’t care when in AAI mode
Data is transmitted to the device least significant nib-
ble first, from byte 0 to byte 127 as long as the RY/BY#
is high and LD# low. The host will pause the clock and
data stream when RY/BY# goes low until it returns
high, signifying that the chip is ready for more data
T19.0 25029
V H
WP#/AAI
LCLK
1 2 3 4 5 6 7 8 9 10 11 12
264
266
(Data Strobe Input)
LFRAME#
Start
MADDR
DATA
DATA
DATA
DATA
DATA DATA
LAD[3:0]
Address
IDSEL
MSIZE
Byte
Byte
Byte
Byte
Byte 0
Byte N
N+1
2N
126
127
LD#
RY/BY#
1237 F08.1
Figure 9: AAI Load Protocol Waveform
?2011 Silicon Storage Technology, Inc.
29
DS25029A
06/11
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